With a requirement to store ever increasing amounts of data within memory, accessing this data in a way that is quick, area efficient and does not have too high a power requirement is an increasing problem. Accessing speeds for memories are dictated by the timing parameters of the memories and the traffic to the memory. Many memories such as DRAM, require lines to be activated before they can be accessed. Activating a line involves large amounts of charge being loaded into the device and the properties of the memory therefore impose a limit on the frequency with which this can be done.
Thus, generally in such memories there is a limit on the number of activate commands that are allowed within a certain amount of time. In order to increase accessing speeds multi-rank DRAM have been provided, in which the different ranks are accessed by the same bus but each rank has its own timing restrictions, such that when one has met the limit for accessing one rank the other can be accessed. However, switching between ranks has its own costs and thus, should be managed carefully.
A further problem with accessing memories that are divided into different ranks or units, each with their own properties, is that accesses to each unit or rank need to be tracked and controlled so that the individual properties of each unit are not violated. Particularly careful tracking needs to be performed in memories such as DRAM where there is no back pressure applied from the memory. Where there are several memory units with their own properties each needs to be tracked. These tracker devices are fairly complex and add to the area of the device, thus as memories scale up and the number of units or ranks increases, providing a tracker for each unit or rank has a heavy area cost.
It would be desirable to be able to provide a memory divided into individual units or ranks such that access timing restrictions can be alleviated without requiring too much additional control circuitry.